The present invention relates to the formation of metal interconnection layers during the manufacture of semiconductor devices, and more particularly to the formation of a damascene structure in a metal interconnect region.
The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor xe2x80x9cchipsxe2x80x9d comprising 5 or more levels of metalization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnect pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading, and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, e.g., a design rule of about 0.18xcexc and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
In prior technologies, aluminum was used in very large scale integration interconnect metalizations. Copper and copper alloys have received considerable attention as a candidate for replacing aluminum in these metalizations. Copper has a lower resistivity than aluminum and improved electrical properties vis-à-vis tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring.
In the formation of a damascene structure, which is used to connect a conductive element to a previously formed metal layer, etching is performed through an insulating layer to create the desired feature, such as a single damascene or dual damascene structure. It is desirable to avoid etching of the underlying metal layer during etching of the overlying dielectric layer. The accidental etching of the metal layer is prevented by the use of an etch stop layer between the metal layer and the dielectric layer. During the etching of the dielectric layer, an etchant recipe is used that exhibits a high selectivity to the dielectric layer, so that the etching essentially stops at the etch stop layer. A second etchant process is performed to remove the etch stop layer in the region within the feature defined by the etching of the dielectric layer. This removes the etch stop layer over the metal layer and allows conductive material deposited in the feature in the dielectric layer to make electrical contact with the metal layer.
U.S. Pat. Nos. 5,693,563 and 5,354,712 describe damascene processes that include the use of copper. An etch stop for a copper damascene process is described in U.S. Pat. No. 5,693,563. The etch stop material that is used, however, as a relatively higher dielectric constant. Since the bulk of the etch stop layer is not removed, as it lies below the dielectric layer, the etch stop layer contributes to a higher overall dielectric value for the total film. This higher dielectric value has an adverse effect on the performance of the device that is ultimately manufactured.
There is a need for a method and arrangement that provides a film with a lower overall dielectric constant value that will exhibit improved overall performance, yet still provides the functionality of an etch stop layer in single damascene and dual damascene manufacturing processes.
These and other needs are met by the present invention which provides a method of forming a damascene structure in a semiconductor device arrangement. The method includes forming an etch stop layer on a metal interconnect layer, where the etch stop layer is composed of a low k dielectric material. A dielectric layer is then formed on the etch stop layer. A feature is etched through the dielectric layer, stopping on the etch stop layer using a first etch recipe. The etch stop layer is then etched through, using a second etch recipe, to enlarge the feature. The etching of the etch stop layer stops on the metal interconnect layer. The feature is then filled with conductive material that contacts the metal interconnect layer. In certain embodiments of the invention, the metal interconnect layer comprises copper, and the etch stop layer comprises benzocyclobutene (BCB).
The earlier stated needs are met by another aspect of the present invention which provides an interconnect arrangement for semiconductor devices comprising a metal interconnect layer and an etch stop layer on the metal interconnect layer. The etch stop layer is composed of a low k dielectric material. The dielectric layer is provided on the etch stop layer. An opening extends through the dielectric layer and the etch stop layer to the metal interconnect layer. Conductive material fills this opening and is in electrically conductive contact with the metal interconnect layer. In certain embodiments of the invention, the metal interconnect layer comprises copper.
The use of an etch stop layer that is composed of low k dielectric material lowers the overall dielectric value of the entire film. This has the advantage of improving the operating performance of the chip. Another important advantage of the use of certain low k materials, such as BCB, in the present invention is the ability of these materials to act as a copper diffusion barrier.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.